The invention relates to high speed analog-to-digital converters, particularly those of the type performing multiple flash encodings of an analog input summed with successive residual voltage voltages obtained by digital-to-analog conversion of successive prior flash encoder outputs.
Various approaches are known for attempting to accomplish high speed analog-to-digital conversion, including use of flash encoders, successive approximation registers (SAR's), and subranging analog-to-digital converters.
FIG. 1 shows a subranging analog-to-digital converter wherein an analog input voltage V.sub.IN is applied to the input 2 of an analog summing circuit 10. The output 12 of summing circuit 10 is applied to each of two amplifiers 14 and 16. Amplifier 14 is a unity gain amplifier, and amplifier 16 has a gain of 2.sup.N, where N is the number of bits of a flash encoder 18 which receives as its analog input the common output 20 of amplifiers 14 and 16 (N=6 in this example).
Six bit flash encoder 18 includes 63 (i.e., 2.sup.N -1) comparators which establish 64 (i.e., 2.sup.N) voltage "windows". The reference voltage V.sub.R applied to the six bit flash encoder 18 is constant. The analog voltage on conductor 20 falls into one of those windows. The comparator output signals are encoded to produce a digital six bit word representative of the analog voltage on conductor 20. In operation, there is a "first pass" wherein amplifier 14 multiplies the value of V.sub.IN on conductor 12 by unity and applies it to the input of flash encoder 18. The six output lines of flash encoder 18 are applied to the six bits of a high precision six bit DAC 22. The highly accurate analog output signal of six bit DAC 22 is fed by conductor 24 into analog summer 10, which produces an output signal that is equal to the difference between V.sub.IN and the voltage on conductor 24.
On the first pass, the most significant six bits of the digital representation of analog input voltage V.sub.IN are converted by six bit DAC 22 to a very accurate (e.g., twelve bits of accuracy) analog voltage on conductor 24. The difference between the voltage on conductor 24 (representing the most significant six bits) and the analog input voltage V.sub.IN produced on conductor 12 is called a "residual voltage".
On a "second pass" of the operation, the residual voltage on conductor 12 is multiplied by the 2.sup.6 gain of amplifier 16. The result on conductor 20 is encoded by six bit flash encoder 18, and the encoded result on conductor 40A is taken as the least significant six bits of the desired twelve bit word. Thus, in two passes V.sub.IN is converted into a 12 bit digital representation thereof, the six most significant bits being obtained on the first pass and the six least significant bits representing the residual voltage being converted on the second pass.
A major disadvantage of the subranging analog-to-digital converter of FIG. 1 is that its speed of operation is limited by high gain amplifier 16. Those skilled in the art know that in linear amplifier theory there is an inherent tradeoff between an amplifier's gain and its bandwidth. For a given technology (for example CMOS technology) a particular implementation of an amplifier will result in a so-called "gain-bandwidth product" of that amplifier. The gain-bandwidth product for an amplifier is constant, so if its gain is increased, its bandwidth decreases accordingly.
Another disadvantage of the subranging analog-to-digital converter of FIG. 1 is that amplifier 16 is complex and requires careful implementation in CMOS technology.